Information processing at a higher speed under a lower operation voltage becomes popular recently, which entails prevention of noise due to electromagnetic radiation from an electronic instrument. One of the methods to reduce the noise is to incorporate a capacitor having dielectric film with a high dielectric constant such as ferroelectric film into an integrated semiconductor circuit, this technique has drawn attention. A study of commercialising a nonvolatile memory is also active, which makes it possible to read and write at a higher speed under a lower operation voltage by using hysterisis characteristic of ferroelectric film.
A conventional semiconductor device incorporated with a ferroelectric capacitor is explained here by referring to the drawings attached. As FIG. 1 shows, isolation oxide layer 2 is formed on silicon substrate 1, and a transistor comprising diffusion layer 3, gate insulating film 4 and gate electrode 5 is formed in the area surrounded by isolation oxide layer 2. A first insulating film 6 covering the transistor and isolation oxide layer 2 is formed.
A capacitor comprising lower electrode 7, ferroelectric film 8 such as lead zirconate titanate (PZT), etc. and upper electrode 9 is formed on the first insulating film 6. Lower electrode 7 and upper electrode 9 are made of platinum which is chemically stable against a metal oxide such as PZT. A second insulating film 11 is formed on the first insulating film 6 to cover thereon.
Contact holes 12 which leads to diffusion layer 3 are formed through the first and second insulating films 6 and 11, and contact holes 13 which lead to lower electrode 7 and upper electrode 9 are formed on the second insulating 11. Both contact holes are formed by etching. Aluminum interconnection layer 14 electrically connected to diffusion layer 3 through contact holes 12 is formed, and aluminum interconnection layer 15 electrically connected to lower electrode 7 as well as upper electrode 9 through contact holes 13 is also formed independently. If lower electrode 7 and upper electrode 9 touch with interconnection layer 15 directly, aluminum reacts with platinum to yield Al.sub.2 Pt during heat treatment, which substantially lowers the connecting strength therebetween. In order to prevent this direct touch, diffusion barrier layer 17 comprising titanium nitride is generally formed in a thickness ranging from 50 nm to 150 nm at the spaces between lower electrode 7 and interconnection layer 15, and upper electrode 9 and interconnection layer 15.
Since silicon substrate 1 where interconnection layers 14 and 15 are formed is in ohmic contact with the interface between interconnection layer 14 and diffusion layer 3, heat treatment at rather higher temperature, higher than 450.degree. C., is given to silicon substrate 1 in inert-gas atmosphere containing hydrogen. And then, passivation layer 16 made of high humid-resisting material such as silicon nitride is formed to cover the transistor and capacitor.
The conventional semiconductor device, with all its diffusion layer 17 having the thickness ranging from 50 nm to 150 nm, connecting strengths at contact holes 13 between lower electrode 7 and interconnection layer 15, and upper electrode 9 and interconnection layer 15 are not sufficient enough. Therefore, some defective continuities occur among many contact holes 13 of a semiconductor device, which proves that the reliability of semiconductor device is not highly enough.